1. Field of the Invention
The invention relates to a sputter mask or stencil used to control deposition of material in a physical vapor deposition (PVD) system. More particularly, the invention relates to a method and apparatus for precise formation of features on the surface of a substrate support chuck used in a process chamber to fabricate a wafer spacing mask upon said substrate support chuck.
2. Description of the Background Art
Substrate support chucks are widely used to support substrates within semiconductor processing systems. More specifically, a semiconductor processing system may have one or more chambers through which the substrates are passed to create a desired product (i.e., a silicon based wafer having IC devices formed thereupon). A chuck is disposed within the chamber to support the substrate and retain it in a stationary position during processing (i.e., etching, deposition and the like). A particular type of chuck is a ceramic electrostatic chuck that is used in high-temperature physical vapor deposition (PVD). Such electrostatic chucks contain one or more electrodes imbedded within a ceramic chuck body. The ceramic material is typically aluminum-nitride or alumina doped with a metal oxide such as titanium oxide (TiO.sub.2) or some other ceramic material with similar resistive properties. This form of ceramic is partially conductive at high temperatures.
In the traditional use of ceramic electrostatic chucks, a wafer rests flush against the surface of the chuck body as a chucking voltage is applied to the electrodes. Because of the conductive nature of the ceramic material at high temperatures, the wafer is primarily retained against the ceramic support surface by the Johnsen-Rahbek effect. Such a chuck is disclosed in U.S. Pat. No. 5,117,121 issued May 26, 1992 and incorporated herein by reference.
One disadvantage of using a chuck body fabricated from ceramic is that, during manufacture, the support surface is "lapped" to smooth the ceramic material. Such lapping produces particles that adhere to the support surface. These particles are very difficult to completely remove from the support surface. The lapping process may also fracture the chuck body. Consequently, as the chuck is used, particles are continuously produced by these fractures. Additionally, during wafer processing, the ceramic material can abrade a wafer oxide coating from the underside of the wafer resulting in further introduction of particulate contaminants to the process environment. During use of the chuck, the particles can adhere themselves to the underside of the wafer and be carried to other process chambers or cause defects in the circuitry fabricated upon the wafer. It has been found that tens of thousands of contaminant particles can adhere to the backside of a given wafer after retention upon a ceramic electrostatic chuck.
To overcome the disadvantages associated with the wafer contacting the substrate support chuck, a wafer spacing mask is deposited upon the surface of the substrate support chuck. Such a wafer spacing mask is disclosed in commonly assigned U.S. Pat. No. 5,656,093 issued Aug. 12, 1997. The material deposited upon the support surface of the chuck body, to form the wafer spacing mask, is a metal or other materials, including conductors, insulators and semiconductors. Usually the material is deposited to form a plurality of pads that support the wafer above the surface of the substrate support. Thus, the wafer spacing mask reduces the amount of contaminant particles that adhere to the underside of the wafer.
A device suitable for forming the spacing mask is disclosed in commonly assigned U.S. patent application Ser. No. 08/736,887 filed Oct. 25, 1996 now U.S. Pat. No. 5,863,396 issued Jan. 26, 1999 and is herein incorporated by reference. FIG. 1 depicts the above-referenced device as a plate-shaped stencil 100 having a plurality of apertures 108 and a plurality of slots 106 although various other configurations are possible. Material is deposited through the apertures 108 and slots 106 (e.g., via physical vapor deposition) to create the desired surface features on the support surface.
It is sometimes necessary to create features on the support surface having different dimensions. For example, some of the deposited pads need to be of a large diameter, or peripheral electrical traces (formed by the slots 106) on the surface need to be longer or wider than a pad (formed by the apertures 108). FIG. 2 depicts a cross-section of the stencil 100 (shown along lines 2--2 of FIG. 1) placed on top of a surface 210 of a ceramic electrostatic chuck 200 following deposition of the surface features by physical vapor deposition. As can be seen, some deposited material 206 forms on the stencil thereby creating no features on the support surface. Some deposited material forms support surface features 204 that have larger dimensions than other features 202. The larger features will generally be thicker in profile as a result of the "shadowing" effect. The "shadowing" effect is a condition by which PVD material approaching the stencil at angles that are not nearly perpendicular to the stencil is deposited on the sidewalls of the aperture instead of the support surface. That is, for smaller features (having narrower stencil openings) less material is deposited on the support surface as compared to a sidewall of the stencil. Conversely, larger features (having wider openings) will be less prone to the "shadowing" effect as more material will deposit on the support surface than on the sidewalls. However, this will cause the larger features to protrude above a desired height "d" on the surface 210. Unfortunately, this condition is undesirable as it leads to non-uniform substrate support, i.e., the point of contact of the various features with the wafer will be at different heights. Non-uniform substrate support alters the critical temperature profile on the wafer and results in excessive bowing of the wafer during chucking. These undesirable conditions eventually alter the quality of the final product.
One possible solution to forming features having uniform profiles (heights) is to create a separate stencil for each feature to be formed. That is, Stencil A consists just of apertures for forming pads, Stencil B consists just of slots for forming peripheral electrical traces and so on. Each stencil then in turn is placed over the support surface and a separate deposition process is executed to form the features specific to the stencil. However, such a method and apparatus is time consuming and requires various stencils which increases overall cost of fabricating the desired support surface features.
Therefore, a need exists in the art for a method and apparatus for fabricating a wafer spacing mask having multiple features wherein the multiple features are formed simultaneously and uniformly in profile.